The next big AI chip battle may not be about processors, but how they are packaged

The race to build more powerful artificial intelligence (AI) chips is creating a new bottleneck in the semiconductor industry: advanced packaging. Companies including Nvidia and AMD are seeking more production capacity as demand for high-performance processors outpaces the industry's ability to package them.

The shift is attracting billions of dollars in investment, with spending on advanced packaging expected to approach $28 billion in 2026, according to research firm Yole Group. Revenue from advanced packaging is also forecast to surpass traditional packaging for the first time this year. What was once a relatively overlooked stage of chip manufacturing is now becoming essential to the development of advanced AI processors.

Why advanced packaging matters for AI chips

Traditional chip packaging mainly protected silicon and provided electrical connections to circuit boards. Advanced packaging does much more. It brings multiple pieces of silicon, including processors and memory, together inside a single package. This allows them to communicate faster and handle the enormous amounts of data required to train and run AI models. Some modern graphics processing units (GPUs) and central processing units (CPUs) can integrate 10 or more chips, with certain designs using as many as 20. Former Intel chief executive Pat Gelsinger told reporters in Taipei that advanced packaging could eventually account for as much as half the value of a chip product. The technology is becoming increasingly important as making processors smaller and adding more transistors becomes harder and more expensive.

Nvidia and AMD look beyond TSMC

Taiwan Semiconductor Manufacturing Company (TSMC), the world's largest contract chipmaker, dominates advanced packaging technology, including its chip-on-wafer-on-substrate (CoWoS) process. Nvidia, AMD and Broadcom use the technology to connect processors with memory and other components.

However, limited capacity at TSMC is encouraging chipmakers to explore additional suppliers. Nvidia is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries (SPIL), a unit of Taiwan's ASE Technology, according to an industry executive familiar with the matter. The funding is expected to support factory expansion and equipment purchases. Nvidia did not respond to a request for comment, while ASE declined to comment on market rumours involving customers. AMD has also announced investments of more than $10 billion across Taiwan's semiconductor industry, including partnerships with ASE, SPIL and Powertech Technology.

Taiwan's packaging alternatives gain attention

Powertech Technology, also known as PTI, is developing panel-level packaging. Unlike conventional wafer-based methods, it uses larger rectangular panels to accommodate more chips in each production run and reduce material waste. The company is working with AMD and Broadcom on the technology. It also plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore, with production potentially beginning in 2028. TSMC is developing its own panel-based approach, called chip-on-panel-on-substrate (CoPoS), and has previously said it built a pilot production line. The expansion is also creating opportunities for semiconductor equipment manufacturers. Companies such as Tokyo Electron and Applied Materials are developing tools to support the growing market. For the AI industry, the message is clear: building powerful processors is no longer enough. Companies must also find ways to package them at scale.