The scan chain mismatch sat at the output like a locked door. In the old workflow, Sashaank Kasturirangan would have spent the better part of a day tracing the chain by hand, then pulling up power state tables in a separate window, hoping the two stories lined up. On this run, the answer came back in minutes. A vendor tool pulled the scan path and the power domain status. An AI layer, trained on the shape of past failures, flagged a missing isolation cell and pointed at the X propagation source.&nbsp;That shift, from days to minutes on a single bug, is the kind of result Kasturirangan has been chasing inside gate-level verification, the pre-tapeout stage where a chip's final netlist is pounded against simulation to catch anything that would turn silicon into scrap. He has built an AI-assisted debug framework that has cut scandump gate-level verification timelines from six to eight weeks down to three to four, roughly a 50 percent reduction in debug time on the projects where it has been deployed.&nbsp;The framework does not touch the simulation or build cycles themselves. Those take what they take. What it changes is the human bottleneck in the middle: an engineer squinting at waveforms, cross-referencing logs, and trying to hold a scan chain's state in their head long enough to form a hypothesis.&nbsp;"Originally scandump gate level verification would take 6 to 8 weeks to catch all bugs in scan chains," Sashaank says. "The waveform analysis and debug would take a whole day sometimes, or at least a few hours."&nbsp;His approach treats the pile of artifacts a modern simulation throws off, waveforms, logs, scan states, power domain information, as raw material to be reshaped before any model sees it. The system converts that mess into structured, context-rich inputs. Then a reasoning layer, built oninternally developed AI tooling and Model Context Protocol integrations from EDA vendors, works through the structured view to isolate root causes: X-propagation sources, broken scan chains, awkward interactions across power domains.&nbsp;The training story matters more than the architecture. Kasturirangan fed the system known failures from across multiple projects. Scan chain shifts that broke mid-pattern. Preshift failures caused by improper backdoor flop randomization of reset signals. Each pattern was documented with the prompt that unlocked it, then folded into a verification framework other engineers could call on. Repeated failure types that used to swallow an hour or two of manual inspection now resolve in minutes.&nbsp;Across projects, he reports a 40 to 65 percent reduction in debug turnaround time, with meaningful gains in first-pass root cause accuracy. The work started inside his own group and has since been shared with other groups for cross-functional pickup.&nbsp;Getting there required a juggling act most verification engineers will recognize. Tapeout schedules do not pause for research projects. Kasturirangan was expected to produce real results on real chips while, in parallel, training a tool that might or might not pay off in time. The bet was that extra hours spent on two early projects would compound later in the pipeline.&nbsp;"Given the complexity of chips and chip manufacturing is ever increasing exponentially with billions of transistors in design nowadays, it is very important to maintain quality while improving efficiency," he says.&nbsp;That constraint shaped the design. He built what he calls a structured debug abstraction layer, a middle tier that separates the messy input data from the reasoning on top. Context-aware patterns written for one design could be reused on the next without rewriting the plumbing. Bringup time on new projects dropped as a result.&nbsp;The scan mismatch case is the one he uses to show skeptics what the workflow actually does. Traditional path: manually trace the scan chain, check power states separately, correlate by eye. New path: the vendor MCP extracts the chain and the power domain OFF status in one pull, and the AI layer identifies the missing isolation and the X source. Hours or days collapse into minutes. The engineer still signs off on the finding, but no longer spends the shift getting there.&nbsp;Kasturirangan is careful about where he thinks this ends up. The automation handles patterns it has seen before, or close relatives of them. Novel bugs, the ones that make tapeout meetings tense, still need someone who understands the fundamentals of design verification to recognize when the AI is confidently wrong.&nbsp;"The future of chip development is going to be radically accelerated with AI assisted flows and debugs," he says, "but an engineer who knows the fundamentals of chip design verification will catch any flaws in the cycle or due to AI inaccuracies and further fine tune the process."For now, he is extending the pattern library, watching how the abstraction layer holds up on larger designs, and tracking which failure classes keep showing up often enough to be worth their own prompt. Each one documented is an hour another engineer will not spend staring at a waveform at midnight

DFT specialist Sashaank Kasturirangan has developed an AI-assisted debug framework that cuts gate-level verification timelines by up to 50 per cent. The system helps engineers identify scan-chain failures, X-propagation and power-domain issues in minutes instead of hours

The scan chain mismatch sat at the output like a locked door. In the old workflow, Sashaank Kasturirangan would have spent the better part of a day tracing the chain by hand, then pulling up power state tables in a separate window, hoping the two stories lined up. On this run, the answer came back in minutes. A vendor tool pulled the scan path and the power domain status. An AI layer, trained on the shape of past failures, flagged a missing isolation cell and pointed at the X propagation source. That shift, from days to minutes on a single bug, is the kind of result Kasturirangan has been chasing inside gate-level verification, the pre-tapeout stage where a chip's final netlist is pounded against simulation to catch anything that would turn silicon into scrap. He has built an AI-assisted debug framework that has cut scandump gate-level verification timelines from six to eight weeks down to three to four, roughly a 50 percent reduction in debug time on the projects where it has been deployed. The framework does not touch the simulation or build cycles themselves. Those take what they take. What it changes is the human bottleneck in the middle: an engineer squinting at waveforms, cross-referencing logs, and trying to hold a scan chain's state in their head long enough to form a hypothesis. "Originally scandump gate level verification would take 6 to 8 weeks to catch all bugs in scan chains," Sashaank says. "The waveform analysis and debug would take a whole day sometimes, or at least a few hours." His approach treats the pile of artifacts a modern simulation throws off, waveforms, logs, scan states, power domain information, as raw material to be reshaped before any model sees it. The system converts that mess into structured, context-rich inputs. Then a reasoning layer, built on internally developed AI tooling and Model Context Protocol integrations from EDA vendors, works through the structured view to isolate root causes: X-propagation sources, broken scan chains, awkward interactions across power domains. The training story matters more than the architecture. Kasturirangan fed the system known failures from across multiple projects. Scan chain shifts that broke mid-pattern. Preshift failures caused by improper backdoor flop randomization of reset signals. Each pattern was documented with the prompt that unlocked it, then folded into a verification framework other engineers could call on. Repeated failure types that used to swallow an hour or two of manual inspection now resolve in minutes. Across projects, he reports a 40 to 65 percent reduction in debug turnaround time, with meaningful gains in first-pass root cause accuracy. The work started inside his own group and has since been shared with other groups for cross-functional pickup. Getting there required a juggling act most verification engineers will recognize. Tapeout schedules do not pause for research projects. Kasturirangan was expected to produce real results on real chips while, in parallel, training a tool that might or might not pay off in time. The bet was that extra hours spent on two early projects would compound later in the pipeline. "Given the complexity of chips and chip manufacturing is ever increasing exponentially with billions of transistors in design nowadays, it is very important to maintain quality while improving efficiency," he says. That constraint shaped the design. He built what he calls a structured debug abstraction layer, a middle tier that separates the messy input data from the reasoning on top. Context-aware patterns written for one design could be reused on the next without rewriting the plumbing. Bringup time on new projects dropped as a result. The scan mismatch case is the one he uses to show skeptics what the workflow actually does. Traditional path: manually trace the scan chain, check power states separately, correlate by eye. New path: the vendor MCP extracts the chain and the power domain OFF status in one pull, and the AI layer identifies the missing isolation and the X source. Hours or days collapse into minutes. The engineer still signs off on the finding, but no longer spends the shift getting there. Kasturirangan is careful about where he thinks this ends up. The automation handles patterns it has seen before, or close relatives of them. Novel bugs, the ones that make tapeout meetings tense, still need someone who understands the fundamentals of design verification to recognize when the AI is confidently wrong. "The future of chip development is going to be radically accelerated with AI assisted flows and debugs," he says, "but an engineer who knows the fundamentals of chip design verification will catch any flaws in the cycle or due to AI inaccuracies and further fine tune the process." For now, he is extending the pattern library, watching how the abstraction layer holds up on larger designs, and tracking which failure classes keep showing up often enough to be worth their own prompt. Each one documented is an hour another engineer will not spend staring at a waveform at midnight

DFT specialist Sashaank Kasturirangan has developed an AI-assisted debug framework that cuts gate-level verification timelines by up to 50 per cent. The system helps engineers identify scan-chain failures, X-propagation and power-domain issues in minutes instead of hours

DFT specialist masters complex chip pre-tapeout trials using AI-assisted gate-level debug

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DFT specialist masters complex chip pre-tapeout trials using AI-assisted gate-level debug